The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Jun. 27, 2019
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Yue Ping Li, Wuhan, CN;

Chun Yuan Hou, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0868 (2016.01); G11C 14/00 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); H01L 27/11 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); G11C 11/56 (2006.01); H01L 27/11526 (2017.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/068 (2013.01); G06F 12/0868 (2013.01); G11C 14/0063 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); H01L 24/05 (2013.01); H01L 24/32 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 27/1104 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/281 (2013.01); G11C 11/5621 (2013.01); G11C 11/5671 (2013.01); H01L 27/11526 (2013.01); H01L 27/11573 (2013.01); H01L 2224/32145 (2013.01);
Abstract

Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N−2)batch of program data, N being an integer equal to or greater than 2, program an (N−1)batch of program data into respective pages in the 3D NAND memory array, and cache an Nbatch of program data in respective space in the on-die cache as a backup copy of the Nbatch of program data.


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