The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Mar. 18, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kevin J. Lee, Beaverton, OR (US);

Yih Wang, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/22 (2006.01); G11C 11/16 (2006.01); H01L 43/06 (2006.01); H01F 41/34 (2006.01); H01L 23/528 (2006.01); H01L 43/04 (2006.01); H01L 43/14 (2006.01); H01L 43/12 (2006.01); H01F 10/32 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); G11C 11/16 (2013.01); G11C 11/161 (2013.01); H01F 10/329 (2013.01); H01F 10/3254 (2013.01); H01F 41/34 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 23/528 (2013.01); H01L 27/22 (2013.01); H01L 27/222 (2013.01); H01L 27/226 (2013.01); H01L 43/04 (2013.01); H01L 43/06 (2013.01); H01L 43/12 (2013.01); H01L 43/14 (2013.01); H01L 29/785 (2013.01);
Abstract

Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells. The spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region. The MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region.


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