The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Jul. 25, 2019
Applicant:

Zhuhai Crystal Resonance Technologies Co., Ltd., Guangdong, CN;

Inventors:

Dror Hurwitz, Zhuhai, CN;

BawChing Perng, Zhuhai, CN;

Duan Feng, Zhuhai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H03H 3/02 (2006.01); H01L 41/313 (2013.01); H01L 41/319 (2013.01); H01L 41/332 (2013.01); H01L 41/337 (2013.01); H01L 41/338 (2013.01); H03H 9/05 (2006.01); H03H 9/10 (2006.01); H03H 9/17 (2006.01);
U.S. Cl.
CPC ...
H03H 3/02 (2013.01); H01L 41/313 (2013.01); H01L 41/319 (2013.01); H01L 41/332 (2013.01); H01L 41/337 (2013.01); H01L 41/338 (2013.01); H03H 9/0523 (2013.01); H03H 9/1042 (2013.01); H03H 9/174 (2013.01); H03H 2003/023 (2013.01);
Abstract

A method for fabricating an array of front ends for an array of packaged electronic components that each comprise: an electrical element packaged within a package comprising a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a 'flip chip' configuration to a circuit board; the method comprising the stages of:


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