The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Aug. 13, 2021
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Purakh Raj Verma, Singapore, SG;

Kuo-Yuh Yang, Hsinchu County, TW;

Chia-Huei Lin, Hsinchu, TW;

Chu-Chun Chang, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 23/58 (2006.01); H01L 23/66 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/564 (2013.01); H01L 21/84 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H01L 23/66 (2013.01); H01L 27/1203 (2013.01); H01L 27/067 (2013.01);
Abstract

A method of forming integrated circuit device, including: providing a substrate; forming an integrated circuit region on the substrate, the integrated circuit region comprising a dielectric stack; forming a seal ring in the dielectric stack and around a periphery of the integrated circuit region; forming a trench around the seal ring and the trench exposing a sidewall of the dielectric stack; forming a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack; and forming a passivation layer over the moisture blocking layer.


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