The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Dec. 03, 2020
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Eugenio Dentoni Litta, Leuven, BE;

Juergen Boemmels, Heverlee, BE;

Julien Ryckaert, Schaerbeek, BE;

Naoto Horiguchi, Leuven, BE;

Pieter Weckx, Bunsbeek, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823871 (2013.01); H01L 21/02603 (2013.01); H01L 21/76224 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 21/823878 (2013.01); H01L 23/5286 (2013.01); H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66515 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.


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