The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

May. 12, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Harish Singidi, Fremont, CA (US);

Kishore Kumar Muchherla, Fremont, CA (US);

Gianni Stephen Alsasua, Rancho Cordova, CA (US);

Ashutosh Malshe, Fremont, CA (US);

Sampath Ratnam, San Jose, CA (US);

Gary F. Besinga, Boise, ID (US);

Michael G. Miller, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/3495 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01);
Abstract

Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.


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