The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Sep. 05, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Kai-Tai Chang, Kaohsiung, TW;

Tung Ying Lee, Hsinchu, TW;

Wei-Sheng Yun, Taipei, TW;

Tzu-Chung Wang, Hsinchu, TW;

Chia-Cheng Ho, Hsinchu, TW;

Ming-Shiang Lin, Hsinchu, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/306 (2006.01); H01L 29/08 (2006.01); H01L 27/088 (2006.01); H01L 21/3105 (2006.01); H01L 21/265 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/30604 (2013.01); H01L 21/76224 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/66636 (2013.01); H01L 21/26513 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/31053 (2013.01); H01L 29/1083 (2013.01); H01L 29/42392 (2013.01);
Abstract

A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.


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