The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Oct. 15, 2020
Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Tsmc Nanjing Company Limited, Nanjing, CN;

Inventors:

Yi-Lin Chuang, Taipei, TW;

Shi-Wen Tan, Nanjing, CN;

Song Liu, Nanjing, CN;

Shih-Yao Lin, Hsinchu, TW;

Wen-Yuan Fang, Nanjing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/392 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01); G06F 30/394 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/373 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01);
Abstract

A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.


Find Patent Forward Citations

Chuang, Yi-Lin. (2022). Method for optimizing floor plan for an integrated circuit (U.S. Patent No. 11443096). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11443096

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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