The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Jul. 31, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Peter McColgan, Dublin, IE;

Baris Ozgul, Dublin, IE;

David Clarke, Dublin, IE;

Tim Tuan, San Jose, CA (US);

Juan J. Noguera Serra, San Jose, CA (US);

Goran H. K. Bilski, Molndal, SE;

Jan Langer, Chemnitz, DE;

Sneha Bhalchandra Date, San Jose, CA (US);

Stephan Munz, Dublin, IE;

Jose Marques, Dublin, IE;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/343 (2020.01); G06F 9/30 (2018.01); G06F 30/398 (2020.01); G06F 30/33 (2020.01);
U.S. Cl.
CPC ...
G06F 30/343 (2020.01); G06F 9/30098 (2013.01); G06F 30/33 (2020.01); G06F 30/398 (2020.01);
Abstract

An integrated circuit includes a plurality of data processing engines (DPEs) DPEs. Each DPE may include a core configured to perform computations. A first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core. The input cascade connection is directly coupled to a plurality of source cores of the plurality of DPEs. The input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is connected to a cascade output of a different one of the plurality of source cores. The input cascade connection is programmable to enable a selected one of the plurality of inputs.


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