The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Jan. 14, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Kun Fang, San Diego, CA (US);

Jaehyun Yeon, San Diego, CA (US);

Suhyung Hwang, Rancho Mission Viejo, CA (US);

Hyunchul Cho, Suwon, KR;

Boyu Tseng, Hsinchu County, TW;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H01L 21/48 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H05K 1/113 (2013.01); H01L 21/486 (2013.01); H05K 1/024 (2013.01);
Abstract

A package that includes a substrate and an electrical component coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, and a solder resist layer located over a surface of the at least one dielectric layer. The solder resist layer includes a first solder resist layer portion comprising a first thickness, and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The electrical component is located over the second solder resist layer portion.


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