The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Dec. 30, 2019
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Liang Chen, Hubei, CN;

Cheng Gan, Hubei, CN;

Wei Liu, Hubei, CN;

Shunfu Chen, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01); H01L 23/64 (2006.01); H01L 49/02 (2006.01); H01L 21/762 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 28/92 (2013.01); H01L 21/76224 (2013.01); H01L 23/528 (2013.01); H01L 23/642 (2013.01); H01L 24/08 (2013.01); H01L 24/89 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80001 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/14511 (2013.01); H01L 2924/19041 (2013.01);
Abstract

Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.


Find Patent Forward Citations

Loading…