The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2022
Filed:
Jul. 16, 2020
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Sheng-Chang Chen, Hsinchu County, TW;
Harry-Hak-Lay Chuang, Zhubei, TW;
Hung Cho Wang, Taipei, TW;
Sheng-Huang Huang, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/22 (2006.01); H01F 10/32 (2006.01); H01F 41/32 (2006.01); H01L 21/768 (2006.01); H01L 43/12 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 43/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); H01F 10/3259 (2013.01); H01F 41/32 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 43/02 (2013.01); H01L 43/12 (2013.01);
Abstract
Some embodiments relate to a method for forming a memory device. The method includes forming a first memory cell over a substrate and forming a second memory cell over the substrate. Further, an inter-level dielectric (ILD) layer is formed over the substrate such that the ILD layer comprises sidewalls defining a first trough between the first memory cell and the second memory cell. In addition, a first dielectric layer is formed over the ILD layer and within the first trough.