The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2022
Filed:
Sep. 24, 2020
Applicant:
Advanced Micro Devices, Inc., Santa Clara, CA (US);
Inventors:
Richard T. Schultz, Fort Collins, CO (US);
John J. Wuu, Fort Collins, CO (US);
Assignee:
Advanced Micro Devices, Inc., Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 27/11 (2006.01); H01L 23/522 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); H01L 23/5226 (2013.01); H01L 27/1108 (2013.01); H01L 27/1116 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01);
Abstract
A layout for a 6T SRAM cell is disclosed. The cell layout takes a conventional 6T SRAM cell layout and restructures the layout into a more square cell layout with a single p-channel and a single n-channel across the width of the cell. Restructuring the cell layout reduces the height of wordlines and allows dual wordlines to be placed in the cell to reduce wordline resistance in the cell. Dual pairs of bitlines may also be placed in separate metal layers in the cell layout to reduce bitline resistance.