The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Aug. 09, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sameer Shekhar, Portland, OR (US);

Amit Kumar Jain, Portland, OR (US);

Kaladhar Radhakrishnan, Chandler, AZ (US);

Jonathan P. Douglas, Portland, OR (US);

Chin Lee Kuan, Pahang, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); G06F 1/20 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); G06F 1/206 (2013.01); H01L 23/49822 (2013.01); H01L 23/5226 (2013.01); H01L 23/5227 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01);
Abstract

Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.


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