The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

May. 17, 2020
Applicant:

Hefechip Corporation Limited, Sai Ying Pun, HK;

Inventor:

Geeng-Chuan Chern, Cupertino, CA (US);

Assignee:

HeFeChip Corporation Limited, Sai Ying Pun, HK;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/24 (2006.01); G11C 11/419 (2006.01); H04L 9/32 (2006.01); G06F 21/72 (2013.01); G11C 17/08 (2006.01); G11C 8/20 (2006.01);
U.S. Cl.
CPC ...
G11C 7/24 (2013.01); G06F 21/72 (2013.01); G11C 8/20 (2013.01); G11C 11/419 (2013.01); G11C 17/08 (2013.01); H04L 9/3278 (2013.01); H04L 2209/12 (2013.01);
Abstract

A physically unclonable function (PUF) circuit includes a program control transistor, a program select transistor, a read select transistor, and a PUF bit storage transistor. The PUF bit storage transistor has a drain region coupled to the read select transistor, a source region coupled to a source line and the program select transistor, a channel region, a gate dielectric layer, and a gate electrode coupled to the program select transistor. The gate dielectric layer has a first portion formed on the drain region, a second portion formed on the source region, and a main portion formed on the channel region and between the first portion and the second portion, thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer being smaller than a thickness of the main portion of the gate dielectric layer.


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