The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2022
Filed:
Mar. 31, 2021
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/31 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/31 (2020.01); G06F 2119/12 (2020.01);
Abstract
Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.
Liu, Miao. (2022). Electronic design 3d mixed placement and unfolding (U.S. Patent No. 11436402). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11436402
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile