The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Jul. 23, 2021
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Tsmc China Company, Limited, Shanghai, CN;

Inventors:

Yaqi Ma, Hsinchu, TW;

Lei Pan, Hsinchu, TW;

JunKui Hu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 3/037 (2006.01); G06F 30/392 (2020.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0185 (2013.01); G06F 30/392 (2020.01); H01L 27/092 (2013.01); H03K 3/037 (2013.01);
Abstract

A circuit includes a bias circuit and a level shifter. The bias circuit includes first and second input terminals configured to receive first and second power supply voltages, and is configured to generate a bias voltage having the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage. The level shifter includes a first PMOS transistor configured to receive the first power supply voltage and a second PMOS transistor configured to receive the second power supply voltage, and each of the first and second PMOS transistors includes a bulk terminal configured to receive the bias voltage.


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