Interconnect structures for logic and memory devices and methods of fabrication

Abstract

An apparatus includes a first interconnect structure above a substrate, a memory device above and coupled with the first interconnect structure in a memory region. The memory device includes a non-volatile memory element, an electrode on the non-volatile memory element, and a metallization structure on a portion of the electrode. The apparatus further includes a second interconnect structure in a logic region above the substrate, where the second interconnect structure is laterally distant from the first interconnect structure. The logic region further includes a second metallization structure coupled to the second interconnect structure and a conductive structure between the second metallization structure and the second interconnect structure. The apparatus further includes a dielectric spacer that extends from the memory device to the conductive structure.