The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Aug. 04, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

S. M. Istiaque Hossain, Boise, ID (US);

Prakash Rau Mokhna Rau, Boise, ID (US);

Arun Kumar Dhayalan, Boise, ID (US);

Damir Fazil, Boise, ID (US);

Joel D. Peterson, Boise, ID (US);

Anilkumar Chandolu, Boise, ID (US);

Albert Fayrushin, Boise, ID (US);

George Matamis, Eagle, ID (US);

Christopher Larsen, Boise, ID (US);

Rokibul Islam, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); G11C 5/02 (2006.01); H01L 21/768 (2006.01); G11C 16/04 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 5/025 (2013.01); G11C 5/06 (2013.01); G11C 16/0466 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01);
Abstract

Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.


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