Sram layout scheme for improving write margin

Abstract

A semiconductor device is provided. The semiconductor can apply different voltages to sources and bases (bulks, N-type well) of pull-up transistors and improves write margin of memory cells. An SRAM of the invention includes P-well regions PW_and PW_, an N-well region NW, a first metal wire M, and a second metal wire M. The P-well regions PW_and PW_extend in a first direction, and pull-down transistors and accessing transistors are formed therein. The N-well region NW extends in first direction, and pull-up transistors are formed therein. The first metal wire Mextends in the first direction on the N-well region NW and is electrically connected to the N-well region NW. The second metal wire Mextends in a second direction orthogonal to the first direction and electrically connected to a common S/D region of a pair of pull-up transistors that are formed in the N-well region NW.