The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Dec. 28, 2018
Applicant:

Tongfu Microelectronics Co., Ltd., Nantong, CN;

Inventor:

Lei Shi, Nantong, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 21/56 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 24/17 (2013.01); H01L 24/33 (2013.01); H01L 24/73 (2013.01);
Abstract

A packaging structure includes a semiconductor chip and conductive connection pillars. Each of the conductive connection pillars has a first surface and a second surface opposite to the first surface, and the first surfaces of the conductive connection pillars are fixed to a surface of the semiconductor chip. The packaging structure also includes a carrier plate. The carrier plate is disposed opposite to the semiconductor chip. The conductive connection pillars are located between the semiconductor chip and the carrier plate, and the second surfaces face the carrier plate. The packaging structure further includes solder layers located between the carrier plate and the second surfaces, and a barrier layer located on the surface of the carrier plate around the solder layers.


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