The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Jul. 24, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Chen Lo, Hsinchu County, TW;

Li-Te Lin, Hsinchu, TW;

Pinyen Lin, Rochester, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/3065 (2006.01); H01L 21/033 (2006.01); H01L 21/027 (2006.01); H01L 29/423 (2006.01); H01L 21/308 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 21/321 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/0274 (2013.01); H01L 21/0337 (2013.01); H01L 21/3065 (2013.01); H01L 21/3086 (2013.01); H01L 21/31122 (2013.01); H01L 21/3212 (2013.01); H01L 21/32136 (2013.01); H01L 21/76832 (2013.01); H01L 29/4236 (2013.01); H01L 29/66553 (2013.01); H01L 29/7851 (2013.01); H01L 29/7848 (2013.01);
Abstract

A semiconductor device includes a substrate, a semiconductor fin, a gate electrode, a pair of gate spacers, a dielectric cap, and a hard mask layer. The semiconductor fin extends upwardly from the substrate. The gate electrode straddles the semiconductor fin. The pair of gate spacers is on opposite sidewalls of the gate electrode. The dielectric cap is atop the gate electrode and laterally between the pair of gate spacers. The hard mask layer is atop the dielectric cap and laterally between the pair of gate spacers. A bottommost position of the hard mask layer is not lower than a topmost position of the dielectric cap.


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