The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2022
Filed:
Mar. 27, 2015
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Jianhui Li, Shanghai, CN;
Yong Wu, Shanghai, CN;
Yihua Jin, Shanghai, CN;
Xueliang Zhong, Shanghai, CN;
Xiao Lin, Shanghai, CN;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 9/455 (2018.01); G06F 9/355 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G06F 9/30174 (2013.01); G06F 9/355 (2013.01); G06F 9/45554 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45583 (2013.01);
Abstract
One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.