The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2022
Filed:
Nov. 29, 2013
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;
Inventor:
Su-Horng Lin, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C23C 16/458 (2006.01); C23C 16/455 (2006.01); C23C 16/44 (2006.01); C30B 25/14 (2006.01); C30B 25/02 (2006.01); C30B 25/16 (2006.01); H01J 37/32 (2006.01); H01L 21/205 (2006.01);
U.S. Cl.
CPC ...
C23C 16/4584 (2013.01); C23C 16/4412 (2013.01); C23C 16/45504 (2013.01); C30B 25/14 (2013.01); C30B 25/02 (2013.01); C30B 25/16 (2013.01); C30B 25/165 (2013.01); H01J 37/3244 (2013.01); H01J 37/32449 (2013.01); H01L 21/205 (2013.01); Y10T 137/0318 (2015.04); Y10T 137/6416 (2015.04);
Abstract
Embodiments of mechanisms for processing a semiconductor wafer are provided. A method for processing a wafer includes providing a wafer process apparatus. The wafer process apparatus includes a chamber and a stage positioned in the chamber for supporting the semiconductor wafer. The method also includes supplying a process gas to the semiconductor wafer via a discharging assembly that is adjacent to the stage. The discharging assembly includes a discharging passage configured without a vertical flow path section.