The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Mar. 25, 2020
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Wen-Fu Huang, Kaohsiung, TW;

Fu-Che Lee, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10894 (2013.01); H01L 21/0217 (2013.01); H01L 21/0223 (2013.01); H01L 21/02126 (2013.01); H01L 21/02164 (2013.01); H01L 21/02167 (2013.01); H01L 21/31111 (2013.01); H01L 27/10805 (2013.01); H01L 27/10897 (2013.01);
Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a logic region; forming a stack structure on the memory region and a gate structure on the logic region; forming a first cap layer on the stack structure and the gate structure; performing an oxidation process to form an oxide layer on the first cap layer; forming a second cap layer on the oxide layer; and removing part of the second cap layer, part of the oxide layer, and part of the first cap layer on the logic region to form a spacer adjacent to the gate structure.


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