Three-dimensional memory device and fabrication method thereof

Abstract

Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed memory device comprises multiple staircase structures stacked over a substrate. The multiple staircase structures are positioned in a dielectric fill structure over the substrate. Each staircase structure comprises multiple gate electrodes separated by multiple insulating layers. The memory device further comprises a semiconductor channel extending from through the multiple staircase structures into the substrate. A first portion of peripheral via structures extends through the dielectric fill structure and is connected to the gate electrodes of each staircase structure. A second portion of peripheral via structures extend through the dielectric fill structure and is connected to a peripheral device over the substrate and neighboring staircase structures.