The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Mar. 18, 2020
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Thomas J. Giovannini, San Jose, CA (US);

Alok Gupta, Fremont, CA (US);

Ian Shaeffer, Los Gatos, CA (US);

Steven C. Woo, Saratoga, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G11C 11/4076 (2006.01); G06F 3/06 (2006.01); G06F 5/06 (2006.01); G06F 1/08 (2006.01); G11C 7/10 (2006.01); G11C 29/02 (2006.01); G06F 13/16 (2006.01); G06F 12/06 (2006.01); G11C 11/409 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/08 (2013.01); G06F 3/0629 (2013.01); G06F 3/0634 (2013.01); G06F 5/06 (2013.01); G06F 12/0646 (2013.01); G06F 13/1689 (2013.01); G11C 7/1078 (2013.01); G11C 7/1087 (2013.01); G11C 7/1093 (2013.01); G11C 11/409 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 11/4096 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.


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