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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11403449 B1

PDFFull Text
Date of Patent:
Aug. 02, 2022

Filed:

Apr. 30, 2021

Systems and methods for configurable switches for verification ip

Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Samarth Saxena, Faridabad, IN;

Raghav Mahajan, Noida, IN;

Kanwarpreet Grewal, Noida, IN;

Neetu Goel, Noida, IN;

Jasleen Kaur, Janakpuri, IN;

Heena Khurana, Sonipat, IN;

Shradha, Bhiwani, IN;

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:

Foley & Lardner LLP

Primary Examiner:

Leigh M Garbowski

Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/3308 (2020.01); G01R 31/3183 (2006.01); G06F 30/333 (2020.01); G06F 30/331 (2020.01); G06F 115/02 (2020.01); G06F 115/06 (2020.01); G06F 115/08 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3308 (2020.01); G01R 31/318357 (2013.01); G06F 30/331 (2020.01); G06F 30/333 (2020.01); G06F 2115/02 (2020.01); G06F 2115/06 (2020.01); G06F 2115/08 (2020.01);
Abstract

An emulator system and a method for emulating functionalities of an integrated circuit design are disclosed. In one aspect, the system includes a plurality of verification components each comprising circuitry configured to perform transactions with at least another verification component. The system can include a plurality of proxies, each executing on a processor and corresponding to a respective one of the verification components. The system can include a switch that is communicatively coupled with the proxies, the switch dynamically configurable to, in a first time duration, operate with a first subset of the proxies to enable a first transaction between a functional module of the design and a first verification component. The switch can be dynamically configurable to, in a second time duration, operate with a second subset of the proxies to enable a second transaction between the functional module and a second verification component.

Find Patent Forward Citations

Saxena, Samarth. (2022). Systems and methods for configurable switches for verification ip (U.S. Patent No. 11403449). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11403449

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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