The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Feb. 08, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aliasgar S. Madraswala, Folsom, CA (US);

Yogesh B. Wakchaure, Folsom, CA (US);

Camila Jaramillo, San Jose, CA (US);

Trupti Bemalkhedkar, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/22 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0613 (2013.01); G06F 3/0634 (2013.01); G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/225 (2013.01); G11C 16/14 (2013.01);
Abstract

A disclosed example to use an erase-suspend feature on a memory device includes a host interface to receive a first erase command to perform an erase operation; and a control circuit to: based on the erase-suspend feature being enabled at the memory device, suspend the erase operation based on determining that a length of time equal to an erase segment duration value has elapsed, the length of time elapsed being relative to a start of an erase segment, and the erase segment duration value specified in a configuration parameter for the erase-suspend feature; perform a second memory operation when the erase operation is suspended; and after the second memory operation is complete, resume the erase operation based on receiving a second erase command from the memory host controller.


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