The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2022

Filed:

Feb. 10, 2020
Applicant:

Sunrise Memory Corporation, Fremont, CA (US);

Inventors:

Tianhong Yan, Saratoga, CA (US);

Scott Brad Herner, Lafayette, CO (US);

Jie Zhou, San Jose, CA (US);

Wu-Yi Henry Chien, San Jose, CA (US);

Eli Harari, Saratoga, CA (US);

Assignee:

SUNRISE MEMORY CORPORATION, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11573 (2017.01); H01L 27/11565 (2017.01); H01L 29/45 (2006.01); H01L 23/528 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/3205 (2006.01); H01L 21/225 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/2251 (2013.01); H01L 21/31111 (2013.01); H01L 21/32053 (2013.01); H01L 23/528 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01); H01L 29/458 (2013.01); H01L 29/665 (2013.01); H01L 29/66742 (2013.01); H01L 29/78642 (2013.01);
Abstract

A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer, and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.


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