The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2022

Filed:

Nov. 30, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Hung-Chang Sun, Kaohsiung, TW;

Akira Mineji, Hsinchu County, TW;

Ziwei Fang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/764 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/311 (2006.01); H01L 21/3105 (2006.01); H01L 21/266 (2006.01);
U.S. Cl.
CPC ...
H01L 21/764 (2013.01); H01L 21/266 (2013.01); H01L 21/26586 (2013.01); H01L 21/31053 (2013.01); H01L 21/31144 (2013.01); H01L 29/515 (2013.01); H01L 29/6656 (2013.01);
Abstract

The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.


Find Patent Forward Citations

Loading…