The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

May. 15, 2020
Applicant:

Montage Technology (Kunshan) Co., Ltd., Jiangsu, CN;

Inventors:

Meng Mei, Suzhou, CN;

Gang Shi, Suzhou, CN;

Peichun Wang, Suzhou, CN;

Guangfeng Li, Suzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/48 (2010.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/94 (2013.01); H01L 2224/1145 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13166 (2013.01);
Abstract

A method for manufacturing an electrical performance test structure of packaged chip, and a method for testing electrical performance of packaged chip, including: providing a first wafer and a second wafer, forming a top metal layer on the first wafer and the second wafer respectively, forming bumps on part of the top metal layer of the first wafer and on part of the top metal layer of the second wafer respectively, removing the top metal layer that is not directly beneath the bumps in the first wafer, and completely retaining the top metal layer in the second wafer, and packaging the first wafer to a first die and packaging the second wafer to a second die, wherein the second die is used as a test structure, and the electrical performance of the second die is used as a reference for electrical performance of the first die.


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