The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Nov. 27, 2019
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Yukinori Sakiyama, West Linn, OR (US);

Edward Augustyniak, Tualatin, OR (US);

Douglas Keil, West Linn, OR (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 16/458 (2006.01); H01L 21/66 (2006.01); H01J 37/32 (2006.01); H01L 21/67 (2006.01); C23C 16/455 (2006.01); C23C 16/509 (2006.01); H01L 21/3065 (2006.01); H01L 21/263 (2006.01); H01L 21/683 (2006.01); C23C 16/50 (2006.01); C23C 16/52 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 22/20 (2013.01); C23C 16/4585 (2013.01); C23C 16/4586 (2013.01); C23C 16/45565 (2013.01); C23C 16/50 (2013.01); C23C 16/509 (2013.01); C23C 16/52 (2013.01); H01J 37/32082 (2013.01); H01J 37/32091 (2013.01); H01J 37/3299 (2013.01); H01J 37/32137 (2013.01); H01J 37/32715 (2013.01); H01J 37/32935 (2013.01); H01L 21/0228 (2013.01); H01L 21/02274 (2013.01); H01L 21/263 (2013.01); H01L 21/3065 (2013.01); H01L 21/67069 (2013.01); H01L 21/67201 (2013.01); H01L 21/683 (2013.01); H01L 22/12 (2013.01); H01J 2237/334 (2013.01); H01L 21/02164 (2013.01);
Abstract

An apparatus for supporting a wafer during a plasma processing operation includes a pedestal configured to have bottom surface and a top surface and a column configured to support the pedestal at a central region of the bottom surface of the pedestal. An electrical insulating layer is disposed over the top surface of the pedestal. An electrically conductive layer is disposed over the top surface of the electrical insulating layer. At least three electrically conductive support structures are distributed on the electrically conductive layer. The at least three support structures are configured to interface with a bottom surface of a wafer to physically support the wafer and electrically connect to the wafer. An electrical connection extends from the electrically conductive layer to connect with a positive terminal of a direct current power supply at a location outside of the pedestal.


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