The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Jun. 23, 2021
Applicant:

Changxin Memory Technologies, Inc., Anhui, CN;

Inventors:

Chuanqi Shi, Hefei, CN;

Heng-Chia Chang, Hefei, CN;

Li Ding, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/18 (2006.01); G11C 29/56 (2006.01); G11C 29/46 (2006.01); G11C 29/40 (2006.01);
U.S. Cl.
CPC ...
G11C 29/56008 (2013.01); G11C 29/18 (2013.01); G11C 29/46 (2013.01); G11C 29/56004 (2013.01); G11C 29/56012 (2013.01); G11C 2029/4002 (2013.01);
Abstract

A memory test method and apparatus, an electronic device, and a computer-readable storage medium are provided. The method includes: obtaining a test instruction; generating, in response to the test instruction, a test clock signal, a to-be-tested address and to-be-tested data; determining a to-be-tested memory from memories of a storage device, the storage device including a self-test circuit; writing the to-be-tested data into a storage unit corresponding to the to-be-tested address of the to-be-tested memory; reading output data from the storage unit corresponding to the to-be-tested address of the to-be-tested memory; and comparing the to-be-tested data and the output data to obtain a test result of the to-be-tested memory. The self-test circuit disposed in the storage device is used to implement a memory test process. Thus, the dependency on automatic test equipment is reduced, thereby improving test speed and reducing test cost.


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