The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2022
Filed:
Feb. 06, 2020
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Chin-Hsiu Huang, Tainan, TW;
Tse-Hsiao Liu, Hsinchu, TW;
Pao-Hao Chiu, Kaohsiung, TW;
Chih-Cherng Liao, Jhudong Township, TW;
Ching-Yi Hsu, Hsinchu, TW;
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Abstract
A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.