The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2022
Filed:
Dec. 13, 2019
Infineon Technologies Ag, Neubiberg, DE;
Oliver Humbel, Maria Elend, AT;
Josef-Georg Bauer, Markt Indersdorf, DE;
Jens Brandenburg, Munich, DE;
Diana Car, Munich, DE;
Philipp Sebastian Koch, Gelugor, MY;
Angelika Koprowski, Klagenfurt, AT;
Sebastian Kremp, Warstein, DE;
Thomas Kurzmann, Villach, AT;
Erwin Lercher, Villach, AT;
Holger Ruething, Munich, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 μm. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.