The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Nov. 06, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Henning Braunisch, Phoenix, AZ (US);

Kemal Aygun, Tempe, AZ (US);

Ajay Jain, Albuquerque, NM (US);

Zhiguo Qian, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/14 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/5383 (2013.01); H01L 24/00 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 23/147 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/215 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/05442 (2013.01);
Abstract

Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.


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