The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Jun. 04, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hui-Min Huang, Taoyuan, TW;

Shou-Cheng Hu, Tai-Chung, TW;

Chih-Wei Lin, Xinfeng Township, TW;

Ming-Da Cheng, Jhubei, TW;

Chung-Shi Liu, Hsinchu, TW;

Chen-Shien Chen, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/495 (2013.01); H01L 21/568 (2013.01); H01L 23/3107 (2013.01); H01L 23/3121 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 24/19 (2013.01); H01L 25/105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48257 (2013.01); H01L 2224/96 (2013.01); H01L 2924/181 (2013.01);
Abstract

A method of packaging a semiconductor die includes connecting an interposer frame directly to a substrate, wherein the interposer frame has a plurality of conductive columns. The method further includes attaching the semiconductor die to the substrate in an opening of the interposer frame, wherein the semiconductor die directly contacts the substrate. The method further includes forming a molding compound to fill space between the semiconductor die and the interposer frame. The method further includes removing a portion of the molding compound to expose the plurality of conductive columns. The method further includes forming a redistribution layer directly contacting a top surface of the semiconductor die and a top surface of the interposer frame.


Find Patent Forward Citations

Loading…