The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Aug. 10, 2020
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Nicolas Posseme, Grenoble, FR;

Cyrille Le Royer, Grenoble, FR;

Fabrice Nemouchi, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823481 (2013.01); H01L 21/28123 (2013.01); H01L 21/76224 (2013.01); H01L 21/823468 (2013.01); H01L 29/6656 (2013.01); H01L 29/7843 (2013.01);
Abstract

A method is provided for producing a component based on a plurality of transistors on a substrate including an active area and an electrical isolation area, each transistor including a gate and spacers on either side of the gate, the electrical isolation area including at least one cavity formed as a hollow between a spacer of a first transistor of the plurality of transistors and a spacer of a second transistor of the plurality of transistors, the first and the second transistors being adjacent, the method including: forming the gates of the transistors; forming the spacers; and forming a mechanically constraining layer for the transistors; and after forming the spacers and before forming the mechanically constraining layer, forming a filling configured to at least partially fill, with a filling material, the at least one cavity within the electrical isolation area, between the spacers of the first and the second transistors.


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