The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Feb. 25, 2020
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Soo Doo Chae, Albany, NY (US);

Sang Cheol Han, Albany, NY (US);

Youngwoo Park, Gyeonggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11524 (2017.01); H01L 21/285 (2006.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); H01L 27/11582 (2013.01); H01L 21/28556 (2013.01); H01L 27/11556 (2013.01);
Abstract

Embodiments provide raised pad formations for step contacts in three-dimensional structures formed on microelectronic workpieces. Steps are formed in a multilayer stack that is used for the three-dimensional structure. The multilayer stack includes alternating non-conductive and conductive layers. For one embodiment, alternating oxide and polysilicon layers are used. The steps expose contact regions on different conductive layers. Material layers are formed on the contact regions to form raised pads. The material layers preferably have a high selectivity with respect to the non-conductive material for etch processes. A protective layer is formed over the steps and the raised pads, and contact holes are formed through the protective layer to the raised pads. Contacts are then formed within the contact holes. The raised pads inhibit punch-through of the non-conductive layers during the forming of the contact holes thereby improving performance of resulting devices formed in the microelectronic workpieces.


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