The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Sep. 04, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Fang Chen, Hsinchu, TW;

Jhon Jhy Liaw, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/06 (2006.01); H01L 27/092 (2006.01); H01L 27/118 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/823878 (2013.01); H01L 27/092 (2013.01); H01L 27/11807 (2013.01); H01L 29/0649 (2013.01); H01L 21/823828 (2013.01);
Abstract

An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.


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