The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2022
Filed:
Jan. 17, 2020
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/09 (2013.01); H01L 21/0217 (2013.01); H01L 21/02118 (2013.01); H01L 21/02282 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01); H01L 23/562 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 2224/023 (2013.01); H01L 2224/0233 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/0236 (2013.01); H01L 2224/02317 (2013.01); H01L 2224/02321 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/05611 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/0613 (2013.01); H01L 2224/06137 (2013.01); H01L 2224/13014 (2013.01); H01L 2224/13101 (2013.01); H01L 2924/1304 (2013.01);
Abstract
A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape. The semiconductor device further includes a second passivation layer configured to stress the at least two PPI lines. The semiconductor device further includes a polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines.