The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2022
Filed:
Oct. 26, 2020
Applicants:
United Microelectronics Corp., Hsin-Chu, TW;
Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;
Inventors:
Assignees:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 29/4991 (2013.01); H01L 21/0214 (2013.01); H01L 27/10891 (2013.01); H01L 29/0657 (2013.01); H01L 29/4236 (2013.01); H01L 29/518 (2013.01);
Abstract
A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.