The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2022
Filed:
Oct. 14, 2020
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Sheng-Chau Chen, Tainan, TW;
Cheng-Tai Hsiao, Tainan, TW;
Cheng-Yuan Tsai, Chu-Pei, TW;
Hsun-Chung Kuang, Hsinchu, TW;
Yao-Wen Chang, Taipei, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 21/311 (2006.01); H01L 21/3105 (2006.01); H01L 43/02 (2006.01); H01L 23/528 (2006.01); H01L 43/08 (2006.01); H01L 43/12 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31116 (2013.01); H01L 21/31053 (2013.01); H01L 21/31055 (2013.01); H01L 23/528 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01); H01L 45/1233 (2013.01); H01L 45/1675 (2013.01); H01L 45/146 (2013.01);
Abstract
A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.