The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2022

Filed:

Jan. 17, 2020
Applicant:

Stmicroelectronics Pte Ltd, Singapore, SG;

Inventors:

Pedro Jr Santos Peralta, Silang, PH;

David Gani, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H01L 21/66 (2006.01); G01R 31/3185 (2006.01); G01R 31/26 (2020.01);
U.S. Cl.
CPC ...
G01R 31/2831 (2013.01); G01R 31/2601 (2013.01); G01R 31/2812 (2013.01); G01R 31/318511 (2013.01); H01L 22/20 (2013.01);
Abstract

A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.


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