The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Dec. 30, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chih-Wei Lin, Taichung, TW;

Chih-Lin Wang, Zhubei, TW;

Kang-Min Kuo, Zhubei, TW;

Cheng-Wei Lian, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/28088 (2013.01); H01L 29/401 (2013.01); H01L 29/42364 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66545 (2013.01); H01L 21/28176 (2013.01); H01L 21/823842 (2013.01); H01L 29/6656 (2013.01);
Abstract

Semiconductor structures and method for forming the same are provided. The method for manufacturing the semiconductor structure includes forming a first gate dielectric layer over a substrate and forming a first capping layer over the first gate dielectric layer. The method for manufacturing the semiconductor structure includes oxidizing the first capping layer to form a first capping oxide layer and forming a first work function metal layer over the first capping oxide layer. The method for manufacturing the semiconductor structure includes forming a first gate electrode layer over the first work function metal layer.


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