The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2022
Filed:
Sep. 01, 2020
Intel Corporation, Santa Clara, CA (US);
Niranjan L. Cooray, Folsom, CA (US);
Abhishek R. Appu, El Dorado Hills, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Joydeep Ray, Folsom, CA (US);
Balaji Vembu, Folsom, CA (US);
Pattabhiraman K, Bangalore, IN;
David Puffer, Tempe, AZ (US);
David J. Cowperthwaite, Portland, OR (US);
Rajesh M. Sankaran, Portland, OR (US);
Satyeshwar Singh, Mather, CA (US);
Sameer Kp, Bangalore, IN;
Ankur N. Shah, Folsom, CA (US);
Kun Tian, Atlanta, GA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.