The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Mar. 19, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Lester Lampert, Portland, OR (US);

James S. Clarke, Portland, OR (US);

Jeanette M. Roberts, North Plains, OR (US);

Ravi Pillarisetty, Portland, OR (US);

David J. Michalak, Portland, OR (US);

Kanwaljit Singh, Rotterdam, NL;

Roman Caudillo, Portland, OR (US);

Hubert C. George, Portland, OR (US);

Zachary R. Yoscovits, Beaverton, OR (US);

Nicole K. Thomas, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/82 (2006.01); H01L 29/49 (2006.01); H01L 29/40 (2006.01); G06N 10/00 (2022.01); H01L 29/423 (2006.01); H01L 21/266 (2006.01); B82Y 10/00 (2011.01); H01L 29/76 (2006.01); H01L 21/265 (2006.01); B82Y 30/00 (2011.01); B82Y 40/00 (2011.01);
U.S. Cl.
CPC ...
H01L 29/66984 (2013.01); B82Y 10/00 (2013.01); G06N 10/00 (2019.01); H01L 21/266 (2013.01); H01L 29/401 (2013.01); H01L 29/423 (2013.01); H01L 29/42376 (2013.01); H01L 29/4983 (2013.01); H01L 29/66075 (2013.01); H01L 29/66439 (2013.01); H01L 29/66977 (2013.01); H01L 29/7613 (2013.01); H01L 29/82 (2013.01); B82Y 30/00 (2013.01); B82Y 40/00 (2013.01); H01L 21/2652 (2013.01); Y10S 977/784 (2013.01); Y10S 977/891 (2013.01); Y10S 977/935 (2013.01);
Abstract

Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.


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