The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

May. 12, 2020
Applicant:

Board of Regents, the University of Texas System, Austin, TX (US);

Inventors:

Sidlgata V. Sreenivasan, Austin, TX (US);

Akhila Mallavarapu, Austin, TX (US);

Jaydeep Kulkarni, Austin, TX (US);

Michael Watts, Austin, TX (US);

Sanjay Banerjee, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 27/11 (2006.01); H01L 21/3065 (2006.01); H01L 29/423 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 27/0886 (2013.01); H01L 27/1104 (2013.01); H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.


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