The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Oct. 09, 2020
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Chia-Hung Chen, Tainan, TW;

Yu-Huang Yeh, Hsinchu, TW;

Chuan-Fu Wang, Miaoli County, TW;

Chin-Chin Tsai, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 21/3212 (2013.01); H01L 21/32133 (2013.01); H01L 27/11568 (2013.01); H01L 29/4234 (2013.01);
Abstract

A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.


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